Embodiments relate to a semiconductor memory cell and methods thereof. Some embodiments relate to a semiconductor memory cell which may be used in a circuit including a silicon substrate biased to a negative potential in a single poly electrically erasable programmable read-only memory (EEPROM) cell, a method of manufacturing the same and/or a method of operating the same.
Referring to example FIG. 1A to FIG. 1C, a single poly EEPROM cell structure is illustrated. A channel hot electron injection scheme may include a particular voltage induced to a floating gate by program voltage +Vp applied to an N-well. A voltage induced to a floating gate may be defined by a coupling ratio. A channel region of an N metal oxide semiconductor (NMOS) may be inverted by a particular voltage induced to a floating gate. Particular voltage VDS may be applied to a drain region of an NMOS, such that current may flow from a drain region toward a source region. Channel hot electrons may be produced in the vicinity of a drain junction region, which may be injected into a floating gate and/or which may result in a relative increase in a threshold voltage of an NMOS device, as illustrated in FIG. 1B.
Referring to FIG. 1C, a view illustrates an erase scheme in a EEPROM according to a Fower-Nordheim (F/N) tunneling method. An N-well may be grounded and/or erase voltage +VE may be applied to a source/drain region of an NMOS. A potential approximating to a ground voltage may be induced to a floating gate by a ground voltage applied to a N-well, and/or an electric field may be relatively strongly biased from a source/drain region of an NMOS toward a floating gate by erase voltage +VE applied to a source/drain region of an NMOS. Electrons existing in a floating gate may be F/N-tunneled by an electric field applied, which may escape into a source/drain region, and/or which may result in a low threshold voltage of an NMOS. Referring to FIG. 1D, a reading operation of a EEPROM is illustrated. Teading voltage +VR may be applied to an N-Well. A particular voltage may be induced to a floating gate. A positive drain voltage, for example, to read may be applied to a drain of an NMOS device. A source of an NMOS device may be grounded.
However, if a threshold voltage of an NMOS device is relatively very high under a programming condition where electrons may be injected in a floating gate, substantially no current may flow since a particular voltage induced to a floating gate may not turn an NMOS device on. In an erase condition where substantially no electrons may be present in a floating gate, current may flow even when a particular voltage induced to a floating gate in a state where a threshold voltage of an NMOS device may be relatively very low may turn an NMOS device on. In a single poly EEPROM, since an N-well may have to be formed to induce a particular potential to a floating gate to program, erase and/or read, a unit cell area may become relatively very large. It may be relatively difficult to implement EEPROM having a high density.